1. Field of the Invention
The invention generally concerns the control of data transmission within real time parallel systems where control is effected by distributing control units throughout the system and, more particularly, a decentralized priority control data transmission system.
Systems of this type comprise a plurality of asynchronous processors or the like which are interconnected in parallel to a bus. Each processor is connected to the bus by an interface, known as a processor coupler or bus controller. This processor coupler, on the one hand, manages data exchange protocols between an originating processor (or requestor) and a terminating processor (or server) and, on the other hand, performs a dynamic priority control.
There are as many couplers as processors; they are all identical. For convenience sake, the association between a processor, a corresponding coupler and an allocator circuit is referred to as a station.
In any system of parallel and asynchronous processors organized around a resource or common resources (in the present case, the bus) conflict situations are inevitable when two or more stations attempt to gain access to the bus simultaneously in order to transmit information to other stations conflicts also occure when the bus becomes free if two or several stations were candidates to use the bus whilst the bus was unavailable because the bus was conveying information.
To preclude access collisions adversely affecting the correct operation of the system as a whole, use is made of arbitration and priority assignment circuity. The arbitration and priority circuitry selects just one of the conflicting stations. Then the arbitration and priority means allocates the bus to the selected station for the time required for that station to propagate its information message. At the end of this period of time, those stations that were previously temporarily rejected make a further attempt to gain access to the bus, thus re-activating the arbitration circuity. The process continues for the waiting stations.
It will also be noted that the multiprocessor systems organized around a bus link readily execute a logic addressing process by diffusion. A station requesting a service, a task, a function, etc. performable by a station in the system may overlook the geographical location and the name (or physical label) of the concerned station or stations in the even of a duplication or multiplication of the stations executing one and the same task for work sharing or operational safety reasons. Indeed, the logic name of the function (service or task) merely has to be transmitted along a DATA bus for the station or stations capable of processing the function, service or task to take account of the request after only one message. The advantages are considerable:
1--there are no software tables associating the logic name of the function with the addresses of the stations capable of performing it to be consulted beforehand.
2--immediate access to an available station conversant with the task to be done without having to resort to a scan search should the first physically addressed station be either overloaded or faulty.
3--quick reconfiguration since there is no up-dating of the software tables mentioned under point 1.
4--possibility for each station of recognizing several logic function addresses.
The difficulty that must be resolved consists of selecting only one station from amongst perhaps many of those capable of performing the function. An arbitration device governing the servers achieves this operation.
2. Description of the Prior Art
L. Nisnevich and E. Strasbourger in "Decentralized Priority Control in Data Communication", Second Annual Symposium on Computer Architecture, Houston, Tex., held from Jan. 20th to 22nd 1975, pages 1 to 6, put forward a scheme for a priority changing system. In this scheme, the bus may be in three states: "transmit 1", "transmit 0", or "no transmission". The "no transmission" signal causes all the active processor couplers to transmit the highest weight (most significant) bit (left most) of their addresses into the bus. In other words, after a message has been transmitted and the bus turns to the "no transmission" state, the active processor couplers start transmitting their own addresses to the bus. If at least one of the transmitted bits is a one then the bus is in the "transmit 1" state, while if all the transmitted bits are zero, the bus is in the "transmit 0" state. The coupler of processor No. i compares the state of the bus with its own weight bit. If the bus is in the "transmit 1" state and coupler No. i has transmitted a "0", then the coupler switches itself off and awaits the next "no transmission" state. Otherwise, coupler No. i remains connected to the bus.
Each processor coupler which remains connected to the bus transmits its second address bit to the bus which turns to a "transmit 1" or "transmit 0" state. All of the processor couplers which have sent the second bit thereof behave as they did following the transmission of the first bit thereof. In other words, if the bus is in the "transmit 1" state all te processor couplers which have sent the "0" signal are switched to off and await the next "no transmission" state. This process is repeated until all the address bits have been transmitted.
After the last bit has been transmitted, only one processor remains connected to the channel (its processor coupler having seized the bus). The address of this processor is greater than the addresses of all of the other couplers that have been trying to occupy the bus during this period.
The drawbacks of this system are that the different processors must be synchronous in order to synchronously transmit the respective address bits of a given weight and that the bus must have a line for each address bit and a line for each processor.